The subject invention is directed generally to circuitry for synchronizing clock signals in a digital system, and more particularly to clock synchronizing circuitry that operates independently of clock signal frequency.
The clock system of a digital system generates clock signals and distributes such clock signals to multiple points of use to synchronize changes in the state of the digital system. The multiple clocks are copies of an external reference clock, and ideally are synchronized or in phase such that all clocked digital devices in a system are clocked at the same instants in time. However, as a result of different insertion delays of circuit components in the clock distribution paths of a clock system, the clocks at the multiple points of use are not synchronized, whereby the active edges of the clock signals do not occur at the same time at the different points of use. As is well known, depending on factors such as clock frequency and the set-up time, hold time, and propagation delay characteristics of the clocked devices, improper data may be stored in clocked devices as a result of the time difference or clock skew between the respective active clock transitions for a sending device and a receiving device that receives data from the sending device.
Clock systems commonly comprise a plurality of clock trees that are driven with a single external master clock, wherein each clock tree provides clock signals to a predetermined group of clocked digital devices. For example, a digital system comprised of a plurality of application specific integrated circuits (ASICs) can have a separate clock tree within each ASIC. For synchronization, the clocks provided by clock trees have been phase locked by use of phase locking circuitry, as for example disclosed in Motorola Application Note AN1509 which discloses a phase compensation technique, a period compensation technique, and an inverted period compensation technique for compensating different delays in the clock signal paths. However, the period compensation techniques, as well as analog phase locked loop methods, are restricted to a limited frequency range and cannot tolerate the use of gated clocks. The phase compensation technique does allow unlimited frequency range and clock gating, but requires that two clocks be distributed.